Fast bandgap reference circuit for use in a low power supply A/D booster

ABSTRACT

A bandgap reference circuit includes a current generation circuit connected to a voltage generation circuit connected to a smart clamping circuit, and a discharge circuit connected to the current generation circuit and the voltage generation circuit. The discharge circuit initially discharges a potential in the current and voltage generation circuits to improve repeatability. A start circuit within the current generation circuit then initializes the reference output at about the supply voltage to improve the speed and settling time of the output signal. The current generation circuit sources a current to the voltage generation circuit that translates the current having a positive function of temperature +T C  into a reference voltage. The smart clamping circuit further generates a clamping voltage having a negative function of temperature −T C  and a load resistance. The clamping voltage and the load resistance are applied across the reference voltage quickly reducing the reference voltage particularly at high temperatures and during start-up to a final level, thereby producing a fast and stable reference voltage.

FIELD OF INVENTION

This invention relates to electronic circuits and more particularlyrelates to voltage and current reference circuits.

BACKGROUND OF THE INVENTION

Voltage and current reference circuits find many applications inelectronic circuits including Flash and other types of electronic memorydevice applications. The bandgap reference circuit is a common circuitsolution for supplying a voltage or current reference for suchapplications. FIG. 1 is a prior art bandgap circuit 100 and operatesgenerally as follows. P1 and P2 act as a standard MOS current mirrorproviding current to Q1 and Q2 which are configured as a bipolar currentmirror. Q1 and Q2 are sized differently; therefore, although theyconduct the same current, they have different current densities.Therefore, there will be a difference in their V_(be) voltages and thedifference will be reflected in the current through R1. VREF is avoltage reference that is a function of the current through R2 and thebase-emitter voltage V_(be) of Q3. Since the current through R2 ismirrored from P1 it is seen that the current through P3 is a function ofΔV_(be) between Q1 and Q2 and R1. Therefore, VREF is a function of theΔV_(be) between Q1 and Q2, the ratio in resistor values R1 and R2, andV_(be) of Q3. The current mirror insures equal currents through Q1 andQ2. Note that Q1 is n times bigger than Q2, thus:ΔV _(be) =V _(BE,Q2) −V _(BE,Q1) =V _(T) In(I _(C) /I _(S))−V _(T) In(I_(C) /nI _(S))=k(T/q)In(n).ΔV_(be) exhibits a positive temperature coefficient (+T_(C)). If thepositive temperature coefficient of ΔV_(be) is combined with V_(BE,Q3),which has a negative temperature coefficient (−T_(C)), along with thecorrect weighting ratios of R1 and R2, VREF will have approximately azero temperature coefficient, and VREF will be independent oftemperature. This ratio is determined by taking the equation for VREFthat incorporates all temperature dependencies, differentiating withrespect to temperature, and setting the equation equal to zero. Forexample, from FIG. 1, we can calculate VREF as:VREF=V _(BE,Q3) +R 2(mI _(C))=V _(BE,Q3) +R 2(mΔV _(be) /R 1)=V _(BE,Q3)+m(R 2/R 1)In(n)kT/q  (1)and:∂VREF/∂T=∂V _(be) /∂T+m(R 2/R 1)In(n)k/q  (2)As discussed, to have a reference that is substantially independent oftemperature, equation (2) should be zero, or:∂VREF/∂T=∂V _(be) /∂T+m(R 2 /R 1)In(n)k/q=0  (2)′If we assume a typical value of positive temperature coefficient for∂V_(be)/∂T:∂V _(be) /∂T=−1.5 mV/° KWhen this value is substituted into equation 2′, and solved for VREF, anew value for VREF is obtained having a zero temperature coefficient,where:VREF=1.25VThis is well known by those skilled in the art of bandgap referencecircuits.

The above explanation of prior art circuit 100 of FIG. 1 assumes thatthe gain-bandwidth product of the reference circuit, temperature,operating speeds, and manufacturing tolerances remain within limitedbounds. However, in many cases, this is not a valid assumption. Often,integrated circuits must operate at, for example, combinations of highspeeds, extreme temperatures, extreme process corners, and low voltages.Under some of these conditions, the gain-bandwidth product of thereference circuit may be inadequate.

Additionally, as device densities and speed requirements continue toincrease, the speed requirement of the bandgap reference circuit mayneed to increase to keep pace with the remainder of the circuit,including a bandgap reference circuit used to supply, for example, thereference voltage for a voltage booster of a memory circuit. Further, assupply voltage levels decrease due to these higher densityarchitectures, device speed requirements may be increasingly difficultto obtain, particularly at low supply voltage and reference levels, andat low operating currents over wide operating temperatures.

It should also be noted that in the typical bandgap reference circuit ofFIG. 1, the current mirror is usually in the cascode form to reduce thevariation of VREF with respect to the supply voltage V_(CC). Theparticular arrangement of bandgap voltage reference of FIG. 1, however,can not be used directly for the high speed boosters being considered,because of reduction in the gain-bandwidth product of the reference athigher speeds and low power supply voltages. Accordingly, there is aneed to provide a means of compensation that reduces the negativeeffects of a low V_(CC) supply voltage applied to a bandgap referencecircuit operating at high speeds and low power supply and referencelevels, while accommodating a wide range of temperature and processvariations.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an extensive overview of the invention. It is intendedneither to identify key or critical elements of the invention nor todelineate the scope of the invention. Rather, its primary purpose is topresent some concepts of the invention in a simplified form as a preludeto the more detailed description that is presented later.

The present invention relates to an electronic circuit and a method forproducing a fast reference voltage or reference current. A bandgapreference circuit includes a current generation circuit connected to avoltage generation circuit that in turn is connected to a smart clampingcircuit. A discharge circuit is further connected to the currentgeneration circuit and the voltage generation circuit. The bandgapreference circuit may be used to supply, for example, the referencevoltage for a voltage booster in a memory circuit. The discharge circuitinitially discharges a residual potential in the current and voltagegeneration circuits to improve repeatability.

A start circuit within the current generation circuit then initializesthe reference output to about the supply voltage to improve the speedand settling time of the output signal. The current generation circuitsources a current to the voltage generation circuit that translates thecurrent that is proportional to a temperature into a reference voltagesignal (FVREF). The smart clamping circuit limits the reference voltageat high temperatures, for example, with a clamping voltage and a loadresistance across the reference voltage. The clamping voltage and theload resistance quickly lowers the reference voltage FVREF to the finallevel, thereby producing a stable, fast reference voltage signal FVREFthat is substantially independent of supply voltage and processvariations.

According to one aspect of the present invention, the discharge circuitcomprises MOS transistors connected to the circuit ground fordischarging any residual potentials which may remain in the current andvoltage generation circuits. This feature improves the settling time andrepeatability of the output reference voltage FVREF.

In another aspect of the invention, the current generation circuitcomprises a current mirror circuit comprising a cascode arrangement offirst and second bipolar and first and second MOS transistors along witha first resistance.

In yet another aspect of the invention, the first resistance of thecurrent generation circuit comprises a poly resistor without silicidethat has a negative temperature coefficient. This provides a referencecurrent having a positive function of temperature to lower the effective∂V_(be)/∂T, which advantageously lowers the FVREF to keep the voltagegeneration circuit operating in saturation particularly at low supplyvoltages, thereby providing voltage reference stability.

In still another aspect of the present invention, a smart clampingcircuit comprises one or more diode-connected transistors and a resistorthat are connected across the output of the voltage generation circuitforming the output of the bandgap reference circuit. The clampingcircuit provides a clamping voltage and a load resistance, that operatesto provide a reference clamping function at high temperatures. Theclamping voltage and the load resistance, quickly limit and lower thereference voltage output FVREF to the final value. The presence of theclamp, although affecting the final value of FVREF, provides a fast andstable reference voltage over a wide range of temperature and supplyvoltage variations.

The aspects of the invention find application in devices that include,for example, high speed voltage booster circuits requiring lowerreference voltages and operating at low supply voltage or low supplycurrent levels, while accommodating a wide range of supply voltages,temperatures and process variations.

To the accomplishment of the foregoing and related ends, the inventioncomprises the features hereinafter fully described and particularlypointed out in the claims. The following description and the annexeddrawings set forth in detail certain illustrative embodiments of theinvention. These embodiments are indicative, however, of but a few ofthe various ways in which the principles of the invention may beemployed. Other objects, advantages and novel features of the inventionwill become apparent from the following detailed description of theinvention when considered in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a prior art bandgap voltagereference circuit 100;

FIG. 2 is system level functional block diagram illustrating anexemplary fast bandgap voltage reference circuit 200, in which variousaspects of the invention may be carried out;

FIG. 3 is schematic diagram illustrating an exemplary fast bandgapvoltage reference circuit 300, in accordance with an aspect of theinvention;

FIG. 4 is a simplified timing diagram 400 illustrating exemplary readmode timings and output of the fast bandgap voltage reference of FIG. 3;and

FIG. 5 is a flow diagram 500 illustrating an exemplary method for a fastbandgap reference operation in association with an aspect of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to thedrawings, wherein like reference numerals are used to refer to likeelements throughout. The present invention relates to an electroniccircuit for producing a fast voltage or current reference which issubstantially independent of V_(CC) fluctuations, and which may be used,for example, to provide a fast low level reference voltage for a voltagebooster for the read mode operations of memory cells. The inventioncomprises current and voltage generation circuits, a smart clampingcircuit, and a discharge circuit.

FIG. 2 illustrates a system level functional block diagram of anexemplary fast bandgap voltage reference circuit 200, for producing afast voltage reference FVREF 205, which may be used, for example, toprovide a fast settling low level reference voltage for a voltagebooster for the read mode operations of memory cells. Fast bandgapcircuit 200 comprises a current generation circuit 210, a voltagegeneration circuit 220 connected to the current generation circuit 210,a smart clamping circuit 230 connected to the voltage generation circuit220, and a discharge circuit 240 connected to the current generationcircuit 210 and the voltage generation circuit 220. A furtherunderstanding of this functional block diagram will be explained ingreater detail in connection with FIG. 3 and following.

Returning to FIG. 2, the V_(CC) power supply and circuit ground isapplied to the bandgap fast voltage reference circuit 200, to supplypower for the reference operation. V_(CC) variations are conventionallyregulated by the current mirror circuit within the current generationcircuit 210 as previously discussed to generate a reference voltageFVREF 205 that is substantially independent of variations in V_(CC).

Initially, discharge circuit 240, comprising, for example, two MOStransistors or other switching elements coupled to circuit ground,provide a discharge path for a residual potential or charge that may bepresent in the voltage and current generator circuits 210, 220 toimprove repeatability in the generation of the reference voltage. Thedischarge circuit 240, activated by the enable bar signal (ENB) 245,discharges any residual potential in the current generation circuit 210via discharge line 250, and a residual potential in the voltagegeneration circuit via discharge line 255 to circuit ground. Dischargecircuit 240 provides repeatable operation each time the referencecircuit is started, and a predictable settling time whether the circuitwas recently activated, or after a long period of inactivity.

The current generation circuit 210 receives enable signal EN 270 tobegin operation, while a start circuit, enabled by a START signal 265(e.g., provided by a control circuit that is not shown), within thecurrent generation circuit 210 initializes the reference output FVREF205 at about the supply voltage V_(CC) to improve the speed and settlingtime of the output signal. The current generation circuit 210 sources astable reference current 260 having a functional relationship totemperature to the voltage generation circuit 220. In the industry,another phrase is coined which states that a given value is“proportional to the absolute temperature” (PTAT). Although a“proportional” or “proportionality” term may also be used in someinstances to describe the relationship between the temperature and aresistance, current, or voltage of the reference circuit, a “functionalrelationship” type term will generally be used herein, in the context ofthe present invention, to gain a broader contextual relationship.However, the use of either term, is not intended to be construed in anylimiting sense. Note: the absolute temperature in accordance with thepresent invention generally refers to a temperature measured in degreesKelvin (° K) relative to absolute zero (e.g., −273° C.).

In the present invention, for example, the current generation circuit210 generates a current having a positive function of temperature (e.g.,a positive temperature coefficient, or +T_(C)). Thus, as the temperatureincreases, for example, the current also increases. The voltagegenerator 220 then translates the +T_(C) reference current 260 from thecurrent generator 210 into a reference voltage FVREF 205.

To quickly bring the reference voltage FVREF 205 to its final value, asmart clamping circuit 230 is also provided. Smart clamping circuit 230,in one example, applies to the reference voltage FVREF 205 a loadresistance, for example, and a clamping voltage in response to a hightemperature. The high temperature clamping voltage and load resistanceare chosen and trimmed, respectively, to produce the final referencevoltage FVREF 205 more quickly than would otherwise occur at hightemperatures without substantially affecting the final value. Thus astable, fast reference voltage signal FVREF 205 is provided that issubstantially independent of supply voltage V_(CC) and processvariations.

In the following FIGS. 3-5 a schematic diagram, timing diagram andmethod flow diagram illustrate an exemplary fast bandgap voltagereference circuit similar to the functional block diagram describedabove for the fast band gap voltage reference circuit 200 of FIG. 2.Although the fast bandgap reference circuit is shown and describedherein with respect to a voltage reference circuit, a current referencecircuit is also anticipated as falling within the scope of the presentinvention.

FIG. 3 illustrates an exemplary fast bandgap voltage reference circuit300, in accordance with an aspect of the invention. Voltage referencecircuit 300, may be used to provide a low supply voltage, fast referencevoltage FVREF 305 for a voltage booster used for the read modeoperations of memory cells as well as in other applications, andoperates similar to that described in FIG. 2. Reference circuit 300 ofFIG. 3 comprises a current generation circuit 310, a voltage generationcircuit 320 connected to the current generation circuit 310, a smartclamping circuit 330 connected to the voltage generation circuit 320,and a discharge circuit 340 connected to the current generation circuit310 and the voltage generation circuit 320.

The voltage reference circuit 300 is enabled with an enable signal ENwhile the complimentary enable bar signal ENB is used to initiatedischarging any residual potential in the current generation circuit 310at circuit node B2 and the voltage generation circuit 320 at circuitnode B3. The voltage reference circuit 300 operation again begins withinthe current generation circuit 310 with a START signal which initializesthe reference output FVREF 305 at about the supply voltage V_(CC) toimprove the speed and settling time of the output signal.

Designing a fast low level reference voltage FVREF 305 (e.g., about1.25V), is difficult when the supply voltage V_(CC) is also low (e.g.,about 1.6V or less). At extreme process corners and temperatures, forexample, the PMOS transistor P3 can go out of the saturation region.Thus, to keep P3 biased into saturation at these low power supplyvoltages, the inventors of the present invention appreciated that thereference voltage FVREF 305 should also be reduced. According to thepresent invention, the FVREF 305 voltage level may be reduced byreducing the “effective” |∂V_(be)/∂T|, which is the effective partialdifferential of the base emitter voltage with respect to temperature.This is done by designing the current I_(C) to be functionally relatedto the temperature. The reference current I_(C) can be calculated as:I _(C) =ΔV _(be) /R 1=((kT/q)In(n))/R 1  (3)

As the silicon bandgap may be impractical to change, the inventorrealized from equation (3) that the current I_(C) may instead, be giventhis functional relationship to temperature in two ways: by making R1 inthe denominator functionally related to the temperature, and by thetemperature T in the numerator. For example, to provide a positivetemperature coefficient (T_(C)) reference current I_(C), a negativetemperature coefficient (−T_(C)) resistor R1 may be used in the currentgeneration circuit 310 to provide a stable reference current I_(C) inresponse to the resistor R1. To produce a resistance with a negativetemperature coefficient, the inventor has used, for example, a polyresistor without silicide that yields a FVREF 305 level of 1.17V with agenerally zero T_(C). At this FVREF level, the P3 transistor can bebiased into saturation at a V_(CC) of 1.6V, as long as the gate drive ofthe diode-connected transistor P1 is less than:1.6V−1.17V=0.43VThis condition can be satisfied by choosing the size of transistors P1and P2 to be sufficiently large.

Thus, the FVREF circuit 300 of the present invention may be used, forexample, to provide a high speed reference with an accuracy of +/−40 mVin a high speed voltage booster circuit. In high speed applications ofthis type, the accuracy may often be traded for the speed of such areference voltage.

According to another aspect of the present invention, the inventorrealized that the settling time of the output voltage FVREF 305 may beshortened by initializing FVREF at about V_(CC). By contrast to a priorart voltage reference circuit, when the VREF is started at groundvoltage, AC performance may be poor as the output voltage typicallytransitions a greater voltage differential to the final output voltage.The inventor has recognized that at extreme process variations,temperature and power supply ranges, a voltage reference circuit canhave significant overshoot or undershoot which makes the repeatabilityof FVREF at these extreme conditions difficult.

Therefore, the inventor has found that by initializing FVREF at aboutV_(CC), that FVREF behaves much more similarly (e.g., going from V_(CC)down to about 1.17V) at these extreme conditions. The START signal used(e.g., START of FIG. 4), is a pulse of about 2-3 ns, for example, and isapplied to the START transistor. With the START signal, the STARTtransistor momentarily grounds the gates of P1, P2, and P3, forces P1,P2, and P3 into full conduction, and momentarily forces the outputvoltage FVREF 305 to about V_(CC).

Accordingly, the reference voltage settles down to the final referencelevel more quickly than with a prior art circuit that starts from theground potential and must rely on the reference current to pull thereference voltage up to the final reference voltage. This techniquerequires less time predominately because the supply voltage is closer tothe final reference voltage than the circuit ground voltage.

The voltage generator 320 is connected to the current generator 310translating the +T_(C) reference current I_(C) into a reference voltageFVREF 305. As previously described, the reference current I_(C) in thereference current generator 310 is mirrored as mic in the voltagegenerator 320 through P3, R2, and Q3 to produce the reference voltageFVREF 305 (wherein m represents a size of P3). The value of FVREF mayfurther be adjusted within the process variations by trimming resistorR2. Thus, according to the present invention, the “effective”|∂V_(be)/∂T|, is made smaller because the reference current I_(C) has a+T_(C) due to the −T_(C) characteristic designed into resistor R1. (seeequation 3 above, having R1 in the denominator).

Although mirror current mI_(C) through P3 increases at hightemperatures, the smart clamping circuit 330 clamps the referencevoltage FVREF to a final reference voltage level. The smart clampingcircuit 330 brings FVREF quickly to the final level, especially at hightemperature, because the V_(BE) of the bipolar transistors decreaseswhen temperature increases. Resistor R3 is used to fine-tune the clampvalue. Resistor R3, therefore, lessens the effect of the clamp on thefinal value of FVREF. In this way, according to the present invention,the smart clamping circuit 330 quickly settles the reference voltageFVREF 305 to a stable final value over a wide range of supply voltagesat high temperatures.

The series combination of diode-connected transistors Q4 and Q5 stronglypull down FVREF toward the final value when FVREF is close to V_(CC),particularly at the higher temperatures where the clamp circuit is mostneeded. The inventor has found that by adjusting R3, the error caused bythe clamp can be controlled within 20 mV of a target reference voltageand still provide its function.

The discharge circuit 340, comprising, for example, two NMOS transistorscoupled to circuit ground, provide an initial discharge path for aresidual potential or charge that may be present in the currentgeneration circuit 310 at circuit node B2 and the voltage generationcircuit 320 at circuit node B3. The discharge circuit 340 providesrepeatable operation each time the reference circuit is started, and apredictable settling time whether the circuit was recently activated, orafter a long period of inactivity. The MOS discharge transistors areactivated by the enable bar signal ENB.

The functionality of circuit 300 of FIG. 3 is now generally described.In the current generator 310, P1 and P2 form a current mirror. Sincethey have the same W/L transistor size ratios they source the sameamount of current. Q1 and Q2 also form a current mirror. However, Q1 andQ2 are sized differently (Q1, in this embodiment, is n times larger thanQ2) to provide different current densities. Thus the current density J2of Q2 is n times larger than the current density J1 in Q1. Thedifference in current density provides a difference in the base-emittervoltage V_(be) of Q1 and Q2. Since:V _(b)(Q 1)=V _(b)(Q 2),thenV _(be)(Q 2)=V _(be)(Q 1)+I _(C)(Q 1)*R 1or,ΔV _(be) =V _(be)(Q 1)−V _(be)(Q 2)=I _(C)(Q 1)*R 1Therefore, the difference in base-emitter voltages of Q1 and Q2 is shownby the voltage existing across R1. In addition to the +T_(C) of theΔV_(be), a −T_(C) resistor is used for R1 to provide a +T_(C)characteristic in I_(C) and mI_(C), which permits a lower referenceoutput voltage FVREF 305 to keep P3 in saturation at low supplyvoltages. The start circuit comprises an NMOS transistor N3 enabled bystart signal START in the present example, to force full conduction ofP1—P3 for starting the FVREF output at about V_(CC) for faster settlingtimes and lower operating current I_(C).

The current I_(C) supplied by P1 to Q1 is mirrored to P3 within thevoltage generator circuit 320. Since, in this particular embodiment, P3and P1 have a W/L size ratio of m/1, P3 conducts a current of mI_(C). P3feeds R2 and Q3 which provide a voltage drop across R2 and a V_(be)(Q3)voltage drop across Q3 because Q3 is biased as a diode.

The enable signal EN drives a PMOS transistor P4 to enable the referencecircuit 300. The enable bar signal ENB (the EN complement) is receivedby, for example, two NMOS transistors N1 and N2 of the discharge circuit340 to discharge any residual voltage potential or charge remaining atthe B2 circuit node of the current generator 310 and B3 circuit node ofthe voltage generator 320. The discharge circuit maintains consistent,repeatable results of the output voltage VREF 305 over large extremes oftemperature, process variations, and supply voltage.

In the smart clamping circuit 330, two diode-connected transistors Q4and Q5 supply the clamping voltage for the reference voltage at highertemperatures, while series resistor R3 lessens the impact of the clampto the final value of FVREF 305. Thus, a bandgap reference voltage isprovided for fast low supply voltage applications that are

substantially independent of extremes of temperature, processvariations, and supply voltage.

FIG. 4 demonstrates an exemplary timing diagram 400 for exemplary readmode timings and output of the fast bandgap voltage reference circuit300 of FIG. 3. The timing of the voltage reference 300 of FIG. 3 isrelative to that of the read access timing 405 which is about 50 ns asdepicted in the timing diagram 400 of FIG. 4.

Prior to a new read access 405 of a new address 415 which begins at timet₀ (420), the enable signal EN 425 applied to the reference circuit 300is low, while its' complimentary signal, enable bar ENB 430 is high.While EN 425 is low, the enable PMOS transistor in the current generator310 pulls the gates of PMOS transistors P1, P2, and P3 to V_(CC) holdingP1, P2, and P3 in an off-state. Simultaneously, complimentary signal ENB430 applied to the two NMOS transistors of the discharge circuit 340 ishigh, forcing the bases of Q1 and Q2 at circuit node B2, and the base ofQ3 at circuit node B3 to discharge any remaining residual potentialwhich may remain from a last reference circuit operation. This reset, orpre-discharge type feature maintains repeatable circuit performance overwide ranges of supply voltage, temperature, and process variations, aswell as a wide range of circuit idle periods.

At time t₀ (420), EN 425 goes high enabling the current generator 310and the voltage generator 320, while complimentary signal ENB 430 goeslow to remove the discharge condition from these circuits. Since speedis a high priority during the read operations, the inventors have alsotaken advantage of the START timing portion of the present invention,wherein the START signal 435 applies a high going pulse of about 2-3 nsto the NMOS START transistor N3 within the current generator circuit310. The NMOS START transistor N3 momentarily pulls the gates of PMOStransistors P1, P2, and P3 to circuit ground, forcing P1, P2, and P3into full conduction, and momentarily pulls the output voltage FVREF(305 of FIG. 3, and 440 of FIG. 4) to about V_(CC) (e.g., about1.6-2.0V). FIG. 4 illustrates three representative curve segments forthe output reference voltage FVREF based on three major groupings ofsupply voltage, temperature conditions, and process variables that maybe found to affect FVREF.

For example, FVREF curve segment 440 represents a median supply voltage,temperature and set of process conditions affecting FVREF. FVREF 440 arepresents a high extreme supply voltage, temperature and set of processconditions, while FVREF 440 b represents a low extreme supply voltage,temperature and set of process conditions affecting FVREF. In oneexemplary testing, the fast bandgap reference voltage circuit of thepresent invention was evaluated using 81 various combinations of supplyvoltage V_(CC) (e.g., 1.6, 1.8, and 2.0V), temperature (e.g., −40, 25,and 100° C.), and process variations (strong, typical, and weak PMOScombined with strong, typical, and weak BJT) wherein the curves shown inFIG. 4 are representative of the exemplary FVREF output test results.

At time t₁ (450), for example, about 2-3 ns after time t₀ (420), STARTsignal 435 returns to a low state, removing the V_(CC) forced pull-up toFVREF 305/440. The current mirror circuit of the current generator 310begins operating to produce a regulated reference current having a+T_(C) due to the −T_(C) resistor R1 and the +T_(C) of the ΔV_(be) inthe current mirror circuit, while the voltage generator 320 translatesthe reference current into a reference voltage FVREF as FVREF approachesa final regulated value 440 c. During this time, the smart clampingcircuit 330, which comprises transistors Q4 and Q5 together with R3,quickly bring the reference voltage FVREF 305/440 down to the finalregulated voltage value 440 c especially at high temperature.

By time t₂ (460), the reference voltage output FVREF 305/440 is at thefinal regulated value 440 c, and is enabled and output to, for example,a voltage booster circuit for a memory read operation. Typically, thismay occur in about 25 ns for a 50 ns read cycle. The read accesscontinues after t₂ (460) for about another 25 ns providing a regulatedreference voltage output FVREF 305/440 for the reference voltage circuit300.

Optionally, between time t₂ (460) and time t₃ (470), about 50 ns after anew address was accessed, enable EN 425 goes low, and enable-bar ENB 430goes high again, and the reference voltage operation of the read accessis completed.

Another aspect of the invention provides a methodology for providing andregulating a reference voltage of a reference operation in an electronicdevice, that may be employed in association with the fast bandgapreference devices illustrated and described herein, as well as withother devices. Referring now to FIG. 5, an exemplary method 500 isillustrated for regulating the reference voltage of a referenceoperation which may be used in a memory device. While the exemplarymethod 500 is illustrated and described herein as a series of acts orevents, it will be appreciated that the present invention is not limitedby the illustrated ordering of such acts or events, as some steps mayoccur in different orders and/or concurrently with other steps apartfrom that shown and described herein, in accordance with the invention.In addition, not all illustrated steps may be required to implement amethodology in accordance with the present invention. Moreover, it willbe appreciated that the method 500 may be implemented in associationwith the apparatus and systems illustrated and described herein as wellas in association with other systems not illustrated.

The method 500 comprises initially discharging any residual voltage orcharge that may be present in current and voltage generator circuits ofa fast bandgap reference voltage circuit, initializing the outputreference voltage to V_(CC). The method 500 further comprises generatinga reference current having a positive function of temperature +T_(C),translating the reference current into a reference voltage, andgenerating a clamping voltage and a load resistance. The clampingvoltage is then applied to the reference voltage to limit the output ofthe reference voltage circuit and quickly settle the reference voltageFVREF to the final level that may be used in a voltage booster circuit.

The fast bandgap reference voltage operation method begins at 502. At504 the current and voltage generator circuits are initially dischargedof any residual potentials to the circuit ground (e.g., 0V), forexample, with a high on the enable bar signal (e.g., ENB of FIG. 3),while the reference voltage circuit is disabled with a low on the enablesignal (e.g., EN of FIG. 3). At 506, the FVREF output (e.g., 305 of FIG.3) of the reference voltage circuit 300 is initialized to about thesupply voltage level (e.g., V_(CC)), for example, with a high on theSTART signal input (e.g., in the current generator circuit 310 of FIG.3). At 508, a base-emitter voltage difference ΔV_(be) is generatedbetween transistors (e.g., Q1 and Q2 of FIG. 3) of a current mirrorcircuit within the current generator 310.

At 510, a resistance of a −T_(C) resistor (e.g., R1 of FIG. 3) is variedin response to the resistor temperature. At 512 the base-emitter voltagedifference ΔV_(be) between transistors Q1 and Q2, is translated into areference current I_(C) having a positive function of temperature +T_(C)in response to the resistance change across R1 and the ΔV_(be). At 514,the +T_(C) reference current I_(C) is translated into a referencevoltage VREF.

At 516, a clamping voltage is generated across the base-emitterjunctions of two diode-connected transistors (e.g., Q4 and Q5 of FIG.3), along with a load resistance (e.g., R3 of FIG. 3). Thereafter at518, the clamping voltage and the load resistance are applied to thereference voltage to quickly limit the reference voltage, particularlyat high temperatures, and provide a fast and stable regulated referencevoltage FVREF (e.g., 305 of FIG. 3) that is substantially independent ofsupply voltage, temperature, and process variations. The fast bandgapreference voltage operation thereafter ends at 520, and the method 500may be repeated for subsequent reference voltage operations of thedevice.

The methodology 500 thus provides for fast, low supply voltage, lowreference voltage circuit that uses a −T_(C) resistor and the +T_(C)ΔV_(be) to create a lower effective partial differential of the baseemitter voltage with respect to the temperature to provide a lowerreference voltage. The method 500 further uses a discharge circuit todischarge any residual potentials from the reference circuit forimproved output repeatability, a start circuit to initialize the FVREFoutput to about V_(CC) for a faster settling time. In addition, themethod 500 uses a smart clamping circuit responsive at hightemperatures, to quickly settle the reference voltage FVREF to a stablefinal value over a wide range of supply voltages. The reference voltageoutput FVREF may be applied to, for example, a voltage booster duringread operations of flash memory arrays. Therefore the method 500generates a reference voltage FVREF that is substantially independent ofvariations in V_(CC) supply voltage, temperature, process corners, andcircuit idle periods. Other variants of methodologies may be provided inaccordance with the present invention, whereby compensation orregulation of a fast reference voltage is accomplished.

Although the invention has been shown and described with respect to oneor more implementations, equivalent alterations and modifications willoccur to others skilled in the art upon the reading and understanding ofthis specification and the annexed drawings. In particular regard to thevarious functions performed by the above described components(assemblies, devices, circuits, etc.), the terms (including a referenceto a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component which performsthe specified function of the described component (i.e., that isfunctionally equivalent), even though not structurally equivalent to thedisclosed structure which performs the function in the hereinillustrated exemplary implementations of the invention. In addition,while a particular feature of the invention may have been disclosed withrespect to only one of several implementations, such feature may becombined with one or more other features of the other implementations asmay be desired and advantageous for any given or particular application.Furthermore, to the extent that the term “includes” is used in eitherthe detailed description and the claims, such term is intended to beinclusive in a manner similar to the term “comprising.”

1. A bandgap reference circuit, comprising: a current generation circuithaving a supply level start-up transistor, the current generationcircuit operable to generate a reference current having a positivefunction of a temperature; a voltage generation circuit connected to thecurrent generation circuit, the voltage generation circuit operable toreceive the reference current from the current generation circuit andproduce a reference voltage in response to the reference current; and asmart clamping circuit connected to the voltage generation circuit,wherein the smart clamping circuit clamps the reference voltage toquickly bring the reference voltage output of the voltage generationcircuit to its final value, thereby producing a fast and stablereference voltage signal; and a discharge circuit connected to thecurrent generation circuit and the voltage generation circuit, thedischarge circuit operable to initially discharge a residual potentialin the current generation circuit and in the voltage generation circuit,the discharge circuit comprising: a first MOS transistor having a firstterminal connected to the current generation circuit, a second terminalconnected to circuit ground, and a control terminal connected to anenable bar input terminal; a second MOS transistor having a firstterminal connected to the voltage generation circuit, a second terminalconnected to circuit ground, and a control terminal connected to theenable bar input terminal and the control terminal of the first MOStransistor; and wherein the first and second MOS transistors areoperable to conduct based on a signal at the control terminals toinitially discharge a residual potential in the current generationcircuit and in the voltage generation circuit, thereby enhancingrepeatability and settling time of the output of the bandgap voltagereference circuit.
 2. The circuit of claim 1, wherein the voltagegeneration circuit comprises: a third MOS transistor having a firstterminal, a second terminal, and a control terminal, wherein the firstterminal is connected to a voltage supply, and the control terminal isconnected to the current generation circuit and the first terminal ofthe start-up transistor; a second resistance having a first terminal anda second terminal, wherein the first terminal is connected to the secondterminal of the third MOS transistor and the second terminal isconnected to circuit ground; and operable to mirror current from thecurrent generation circuit using the third MOS transistor as a currentmirror and translate the current from the current generation circuit toa voltage by conducting the current through the second resistance,whereby the first terminal of the second resistance forms the output ofthe bandgap voltage reference circuit.
 3. The circuit of claim 1,wherein the current generation circuit comprises: a current mirrorhaving a first leg and a second leg; a first bipolar transistor having acollector terminal connected to the first leg of the current mirror, anemitter terminal connected to circuit ground, and a base terminal; asecond bipolar transistor having a collector terminal connected to thesecond leg of the current mirror, a base terminal connected to the baseterminal of the first bipolar transistor, and an emitter terminal, thefirst bipolar transistor having a different size than the second bipolartransistor; a first resistance having a first terminal and a secondterminal, the first terminal connected to the emitter terminal of thefirst bipolar transistor and the second terminal connected to circuitground; a supply level start-up transistor having a first terminal, asecond terminal, and a control terminal, the first terminal connected tothe first leg of the current mirror, the voltage generation circuit, andthe base terminals of MOS transistors for the current mirror and thevoltage generation circuit, the second terminal connected to circuitground, and the control terminal connected to a start-up input terminal,wherein the supply level start-up transistor initially provides basedrive to the MOS transistors for substantially full conduction in thecurrent mirror and the voltage generation circuit to start the referencecircuit at about the level of the supply voltage; and operable togenerate a current in the first leg of the current mirror that is afunction of a difference in the base-emitter voltages of the first andsecond bipolar transistors and a magnitude of the first resistance. 4.The circuit of claim 3, wherein the first resistance comprises apolysilicon material having a negative temperature coefficient, whereinthe reference current having the positive function of the temperature isprovided.
 5. The circuit of claim 3, wherein the current mirrorcomprises: a first MOS transistor having a first terminal, a secondterminal, and a control terminal, wherein the first terminal isconnected to the supply voltage, the second terminal is connected to thecollector terminal of the first bipolar transistor and forms the firstleg of the current mirror, and a control terminal connected to thesecond terminal of the first MOS transistor; and a second MOS transistorhaving a first terminal, a second terminal, and a control terminal,wherein the first terminal is connected to the voltage supply, thesecond terminal is connected to the collector terminal of the secondbipolar transistor and forms the second leg of the current mirror, and acontrol terminal connected to the control terminal of the first MOStransistor.
 6. The circuit of claim 5, wherein the second resistancecomprises: a resistor having a first terminal and a second terminal,wherein the first terminal forms the first terminal of the secondresistance; and a diode having an anode and a cathode, wherein the anodeis connected to the second terminal of the resistor, and the cathodeforms the second terminal of the second resistance.
 7. The circuit ofclaim 6, wherein the diode comprises a bipolar transistor having acollector terminal, a base terminal, and an emitter terminal, whereinthe collector terminal is connected to the base terminal and forms theanode of the diode and the emitter terminal forms the cathode of thediode.
 8. A bandgap reference circuit, comprising: a current generationcircuit having a supply level start-up transistor, the currentgeneration circuit operable to generate a reference current having apositive function of a temperature; a voltage generation circuitconnected to the current generation circuit, the voltage generationcircuit operable to receive the reference current from the currentgeneration circuit and produce a reference voltage in response to thereference current; and a smart clamping circuit connected to the voltagegeneration circuit, wherein the smart clamping circuit clamps thereference voltage to quickly bring the reference voltage output of thevoltage generation circuit to its final value, thereby producing a fastand stable reference voltage signal; wherein the smart clamping circuitcomprises: a third resistor having a first terminal and a secondterminal, wherein the first terminal forms the first terminal of thesecond resistance of the voltage generation circuit and the output ofthe bandgap voltage reference circuit; first and second diodes connectedin series, each diode having an anode and a cathode, wherein the anodeof the first diode is connected to the second terminal of the thirdresistor, the cathode of the first diode is connected to the anode ofthe second diode, and the cathode of the second diode is connected tocircuit ground; and operable to quickly bring the reference voltageoutput of the voltage generation circuit to its final value, wherein avoltage drop across the first and second diodes provides a portion ofthe clamping voltage and the voltage drop across the third resistorcontrols a voltage error associated with the clamping circuit, andwherein the clamping circuit provides a variable voltage limit for theclamping of the reference voltage in response to the temperature of thefirst and second diodes.
 9. A method of providing a stable referencesignal, comprising: discharging a residual potential at a first bipolartransistor and at a first diode; initializing the reference signal atabout a voltage level of the supply voltage; generating a base-emittervoltage difference between a base-emitter voltage of the first bipolartransistor and a base-emitter voltage of a second bipolar transistor;varying a resistance of a negative temperature coefficient resistorhaving a negative function of a temperature of the resistor; translatingthe difference in base-emitter voltages of the two bipolar transistorsinto a reference current having a positive function of the temperature,wherein the reference current is a function of the difference inbase-emitter voltages of the two bipolar transistors and the resistanceof a negative temperature coefficient resistor having a negativefunction of the resistor temperature; translating the reference currenthaving a positive function of the temperature to a reference voltage;generating a clamping voltage and a load resistance; and applying theclamping voltage and the load resistance to the reference voltage,wherein the clamping and loading of the reference voltage produces afast and stable reference signal that is substantially independent ofvariations in supply voltage, and process variations; wherein generatinga clamping voltage and a load resistance comprises: providing a voltageacross a base-emitter junction of one or more diode-connectedtransistors; exposing the one or more diode-connected transistors to thetemperature; generating a voltage across the one or more diode-connectedtransistors; applying the reference voltage from the voltage generationcircuit to a load resistor and the one or more diode-connectedtransistors, wherein the load resistor and the one or morediode-connected transistors form a smart clamping circuit; generating avoltage difference across the load resistor based on the sum of thereference voltage and the voltage across the one or more diode-connectedtransistors; and wherein the voltage difference across the load resistorprovides a variable load current to the reference voltage, wherein theclamping and loading of the reference voltage forms a stable referencesignal that is substantially independent of variations in supplyvoltage, and process variations.
 10. The method of claim 9, whereingenerating a base-emitter voltage difference comprises: conducting afirst current through the first bipolar transistor, the first bipolartransistor exhibiting a first current density; and conducting a secondcurrent through the second bipolar transistor, the second bipolartransistor exhibiting a second current density, wherein the firstcurrent is approximately equal in magnitude to the second current andthe first current density to larger than the second current density. 11.The method of claim 9, wherein the translating the difference betweenthe base-emitter voltages of the first bipolar transistor and the secondbipolar transistor into a reference current comprises the step ofplacing the difference between the base-emitter voltages of the firstbipolar transistor and the second bipolar transistor across a negativetemperature coefficient resistance, wherein the reference current is afunction of the magnitude of the difference between the base-emittervoltages of the first bipolar transistor and the second bipolartransistor, the magnitude of the resistance, the magnitude of thenegative temperature coefficient of the resistor, and the magnitude ofthe temperature.
 12. The method of claim 9, wherein varying a resistanceof a negative temperature coefficient resistor having a negativefunction of a temperature of the resistor comprises exposing theresistor to the temperature.
 13. The method of claim 9, whereingenerating a clamping voltage comprises: providing a voltage across adiode junction or a diode-connected transistor; and exposing the diodeor diode-connected transistor to the temperature.
 14. The method ofclaim 9, wherein translating the reference current having a positivefunction of the temperature to a reference voltage comprises: applyingthe reference current to the base of an appropriately sized first MOStransistor in a voltage generation circuit; providing a voltage across abase-emitter junction of a diode-connected transistor; exposing thediode-connected transistor to the temperature; generating a voltageacross a resistor and the diode-connected transistor of the voltagegeneration circuit in response to the temperature of the diode-connectedtransistor; and wherein a voltage produced at a connection between thefirst MOS transistor and the resistor within the voltage generationcircuit forms the reference voltage.
 15. A bandgap reference circuit,comprising: a current generation circuit operable to generate areference current having a positive function of a temperature; a voltagegeneration circuit connected to the current generation circuit, thevoltage generation circuit operable to receive the reference currentfrom the current generation circuit and produce a reference voltage inresponse to the reference current; a smart clamping circuit connected tothe voltage generation circuit, wherein the smart clamping circuitclamps the reference voltage to quickly bring the reference voltageoutput of the voltage generation circuit to its final value, therebyproducing a fast and stable reference voltage signal; and a dischargecircuit connected to the current generation circuit and the voltagegeneration circuit, the discharge circuit operable to initiallydischarge a residual potential in the current generation circuit and inthe voltage generation circuit, the discharge circuit comprising: afirst MOS transistor having a first terminal connected to the currentgeneration circuit, a second terminal connected to circuit ground, and acontrol terminal connected to an enable bar input terminal; a second MOStransistor having a first terminal connected to the voltage generationcircuit, a second terminal connected to circuit ground, and a controlterminal connected to the enable bar input terminal and the controlterminal of the first MOS transistor; and wherein the first and secondMOS transistors are operable to conduct based on a signal at the controlterminals to initially discharge a residual potential in the currentgeneration circuit and in the voltage generation circuit, therebyenhancing repeatability and settling time of the output of the bandgapvoltage reference circuit.
 16. The circuit of claim 15, wherein thecurrent generation circuit comprises: a current mirror having a firstleg and a second leg; a first bipolar transistor having a collectorterminal connected to the first leg of the current mirror, an emitterterminal connected to circuit ground, and a base terminal; a secondbipolar transistor having a collector terminal connected to the secondleg of the current mirror, a base terminal connected to the baseterminal of the first bipolar transistor, and an emitter terminal, thefirst bipolar transistor having a different size than the second bipolartransistor; a first resistance having a first terminal and a secondterminal, the first terminal connected to the emitter terminal of thefirst bipolar transistor and the second terminal connected to circuitground; a supply level start-up transistor having a first terminal, asecond terminal, and a control terminal, the first terminal connected tothe first leg of the current mirror, the voltage generation circuit, andthe base terminals of MOS transistors for the current mirror and thevoltage generation circuit, the second terminal connected to circuitground, and the control terminal connected to a start-up input terminal,wherein the supply level start-up transistor initially provides basedrive to the MOS transistors for substantially full conduction in thecurrent mirror and the voltage generation circuit to start the referencecircuit at about the level of the supply voltage; and operable togenerate a current in the first leg of the current mirror that is afunction of a difference in the base-emitter voltages of the first andsecond bipolar transistors and a magnitude of the first resistance. 17.The circuit of claim 16, wherein the current mirror comprises: a firstMOS transistor having a first terminal, a second terminal, and a controlterminal, wherein the first terminal is connected to the supply voltage,the second terminal is connected to the collector terminal of the firstbipolar transistor and forms the first leg of the current mirror, and acontrol terminal connected to the second terminal of the first MOStransistor; and a second MOS transistor having a first terminal, asecond terminal, and a control terminal, wherein the first terminal isconnected to the voltage supply, the second terminal is connected to thecollector terminal of the second bipolar transistor and forms the secondleg of the current mirror, and a control terminal connected to thecontrol terminal of the first MOS transistor.
 18. The circuit of claim16, wherein the first resistance comprises a polysilicon material havinga negative temperature coefficient, wherein the reference current havingthe negative function of the temperature is provided.
 19. The circuit ofclaim 15, wherein the voltage generation circuit comprises: a third MOStransistor having a first terminal, a second terminal, and a controlterminal, wherein the first terminal is connected to a voltage supply,and the control terminal is connected to the current generation circuitand the first terminal of the start-up transistor; a second resistancehaving a first terminal and a second terminal, wherein the firstterminal is connected to the second terminal of the third MOS transistorand the second terminal is connected to circuit ground; and operable tomirror current from the current generation circuit using the third MOStransistor as a current mirror and translate the current from thecurrent generation circuit to a voltage by conducting the currentthrough the second resistance, whereby the first terminal of the secondresistance forms the output of the bandgap voltage reference circuit.20. The circuit of claim 19, wherein the second resistance comprises: aresistor having a first terminal and a second terminal, wherein thefirst terminal forms the first terminal of the second resistance; and adiode having an anode and a cathode, wherein the anode is connected tothe second terminal of the resistor, and the cathode forms the secondterminal of the second resistance.
 21. The circuit of claim 20, whereinthe diode comprises a bipolar transistor having a collector terminal, abase terminal, and an emitter terminal, wherein the collector terminalis connected to the base terminal and forms the anode of the diode andthe emitter terminal forms the cathode of the diode.
 22. A bandgapreference circuit, comprising: a current generation circuit operable togenerate a reference current having a positive function of atemperature; a voltage generation circuit connected to the currentgeneration circuit, the voltage generation circuit operable to receivethe reference current from the current generation circuit and produce areference voltage in response to the reference current; a smart clampingcircuit connected to the voltage generation circuit, wherein the smartclamping circuit clamps the reference voltage to quickly bring thereference voltage output of the voltage generation circuit to its finalvalue, thereby producing a fast and stable reference voltage signal; anda current generation circuit having a supply level start-up transistor,the current generation circuit operable to generate a reference currenthaving a positive function of a temperature comprising: a MOS transistorhaving a first terminal, a second terminal, and a control terminal, thefirst terminal connected to the current generation circuit, and thevoltage generation circuit, the second terminal connected to circuitground, and the control terminal connected to a start-up input terminal,wherein the supply level start-up transistor initially producessubstantially full conduction in the current and voltage generationcircuits to start the reference circuit at about the level of the supplyvoltage.
 23. A bandgap reference circuit, comprising: a currentgeneration circuit operable to generate a reference current having apositive function of a temperature; a voltage generation circuitconnected to the current generation circuit, the voltage generationcircuit operable to receive the reference current from the currentgeneration circuit and produce a reference voltage in response to thereference current; a smart clamping circuit connected to the voltagegeneration circuit, wherein the smart clamping circuit clamps thereference voltage to quickly bring the reference voltage output of thevoltage generation circuit to its final value, thereby producing a fastand stable reference voltage signal, wherein the smart clamping circuitcomprises: a third resistor having a first terminal and a secondterminal, wherein the first terminal forms the first terminal of thesecond resistance of the voltage generation circuit and the output ofthe bandgap voltage reference circuit; first and second diodes connectedin series, each diode having an anode and a cathode, wherein the anodeof the first diode is connected to the second terminal of the thirdresistor, the cathode of the first diode is connected to the anode ofthe second diode, and the cathode of the second diode is connected tocircuit ground; and operable to quickly bring the reference voltageoutput of the voltage generation circuit to its final value, wherein avoltage drop across the first and second diodes provides a portion ofthe clamping voltage and the voltage drop across the third resistorcontrols a voltage error associated with the clamping circuit, andwherein the clamping circuit provides a variable voltage limit for theclamping of the reference voltage in response to the temperature of thefirst and second diodes.